`timescale 1ns/1ps
module circuit2_top ;
    reg clk,w,reset;
    always # 1 clk = ~clk;
    initial begin
        clk = 0;
        reset = 0;
        w = 0;
        # 1 reset = 1 ;
        # 2 reset = 0 ;
        # 3 w =1;
        # 10 w=0;
        # 8 w=1;
        # 10 w=0;
        # 2 reset = 0;
        # 2 $finish;
    end
    circuit2 c2(z,w,clk,reset);
initial
  	begin
    	$dumpfile("test.vcd");
    	$dumpvars(0, c2);
  	end 
endmodule


module circuit2(z,w,Clock,reset);
	input w,Clock,reset;
    output z;
    reg Q1,Q2;
    wire D1,D2;
    assign z = Q1 & (~Q2);
    assign D1 = w & (Q1 | Q2);
    assign D2 = w & (~Q2 | ~Q1);
   	always @(posedge Clock or posedge reset)begin
        if(reset)begin
        	Q1 <= 1'b0;
        	Q2 <= 1'b0;	
        end
        else begin
        	Q1 <= D1;
       		Q2 <= D2;
        end
    end        
endmodule
